Programmable Logic and VHDL

1. Functional Requirements and Constraints
2. a) A simple system that places an ascending binary count on leds at selectable count rates is to be designed.
3. b) A 2-bit value ‘x’ is to be read from the two least significant dil switches on the DE0-nano board.
4. c) The leds on the DE0-nano board should show an ascending binary count with a least significant bit count period being ‘x’ seconds where x is an integer between 1 and 7.

2.c Design and Test Methodology

1. a) The hardware should be designed by firstly splitting up the overall task into functional blocks.
2. b) Each block may then be defined (inputs, outputs and process).
3. c) The blocks may then be implemented in VHDL and simulated.
4. d) The code may then be downloaded and tested on the DE2 board.